The semiconductor industry continually strives to increase device performance by reducing the distance between individual devices, and by reducing the size of the devices themselves. Unfortunately, this continuing reduction in device dimensions has begun to adversely effect the performance and the reliability of integrated circuits. More specifically, as the device density increases more levels of metallization are required to interconnect the different devices. The plasma processes currently used to form the various levels of metallization, however, often damage the scaled devices. For example, the plasma processes currently used to etch contact or via openings often cause the thin gate oxide used in high performance semiconductor devices to rupture.
Accordingly, a need exists for a method to form interconnect structures which minimizes process induced damage to the integrated circuit.